{
  "cveId": "CVE-2025-37964",
  "url": "https://patchblox.com/security/cve/CVE-2025-37964",
  "summary": "CVE-2025-37964 is fixed in 68 products on 1 platform, first by DEBIAN-CVE-2025-37964, released May 20, 2025. It is not reported as exploited. Patch Radar priority: High.",
  "title": "linux: In the Linux kernel, the following vulnerability has been resolved:  x86/mm: Eliminate window where TLB flushes may b...",
  "description": "In the Linux kernel, the following vulnerability has been resolved:  x86/mm: Eliminate window where TLB flushes may be inadvertently skipped  tl;dr: There is a window in the mm switching code where the new CR3 is set and the CPU should be getting TLB flushes for the new mm.  But should_flush_tlb() has a bug and suppresses the flush.  Fix it by widening the window where should_flush_tlb() sends an IPI.  Long Version:  === History ===  There were a few things leading up to this.  First, updating mm_cpumask() was observed to be too expensive, so it was made lazier.  But being lazy caused too many unnecessary IPIs to CPUs due to the now-lazy mm_cpumask().  So code was added to cull mm_cpumask() periodically[2].  But that culling was a bit too aggressive and skipped sending TLB flushes to CPUs that need them.  So here we are again.  === Problem ===  The too-aggressive code in should_flush_tlb() strikes in this window:  \t// Turn on IPIs for this CPU/mm combination, but only \t// if should_flush_tlb() agrees: \tcpumask_set_cpu(cpu, mm_cpumask(next));  \tnext_tlb_gen = atomic64_read(\u0026next-\u003Econtext.tlb_gen); \tchoose_new_asid(next, next_tlb_gen, \u0026new_asid, \u0026need_flush); \tload_new_mm_cr3(need_flush); \t// ^ After \u0027need_flush\u0027 is set to false, IPIs *MUST* \t// be sent to this CPU and not be ignored.          this_cpu_write(cpu_tlbstate.loaded_mm, next); \t// ^ Not until this point does should_flush_tlb() \t// become true!  should_flush_tlb() will suppress TLB flushes between load_new_mm_cr3() and writing to \u0027loaded_mm\u0027, which is a window where they should not be suppressed.  Whoops.  === Solution ===  Thankfully, the fuzzy \u0022just about to write CR3\u0022 window is already marked with loaded_mm==LOADED_MM_SWITCHING.  Simply checking for that state in should_flush_tlb() is sufficient to ensure that the CPU is targeted with an IPI.  This will cause more TLB flush IPIs.  But the window is relatively small and I do not expect this to cause any kind of measurable performance impact.  Update the comment where LOADED_MM_SWITCHING is written since it grew yet another user.  Peter Z also raised a concern that should_flush_tlb() might not observe \u0027loaded_mm\u0027 and \u0027is_lazy\u0027 in the same order that switch_mm_irqs_off() writes them.  Add a barrier to ensure that they are observed in the order they are written.",
  "published": "2025-05-20T16:15:34Z",
  "severity": "medium",
  "cvss": 7,
  "cvssVector": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H",
  "epss": 0.00209,
  "epssPercentile": 0.11131,
  "priority": "High",
  "priorityTier": 3,
  "exploited": false,
  "vendorExploited": false,
  "disclosed": false,
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